Memory and 3D Test
Primary test platforms available at STATS ChipPAC for Memory Test Click here to request the availability of other memory test platforms at STATS ChipPAC.
Focus and Commitment to Memory Test
As the leader in 3D package assembly, STATS ChipPAC is committed to extend this dominance into test. We have achieved this by:
- Installing Memory Test systems and solutions most requested by customers.
- Establishing Memory Test experts in its Test Development Center for development of test programs, probe cards and load boards for Memory devices and 3D devices with Memory components.
- Maximizing throughput for 3D devices that include Memory components by optimizing the number of test stages and test platform mix with no loss in test coverage.
- Delivering Memory Test solutions that provide the lowest cost of test.
- Enabling full turnkey assembly and test solutions for Memory products to further lower the overall costs of manufacturing.
High Throughput
STATS ChipPAC’s Shanghai factory (SCC) is already at the frontier of high throughput testing of 640 Flash Memory devices in parallel in high volume production.
The adjacent photo shows a row of Mirae handlers testing Memory devices with high parallelism and high throughput on the test floor of STATS ChipPAC Shanghai. STATS ChipPAC Shanghai uses a Mirae M520 handler to enable high parallel test setups up to 640 test sites and higher. Even higher levels of parallelism are possible if the tester has sufficient resources to test all the devices at the same time.
To complement its high parallel testing capabilities at package test, STATS ChipPAC Shanghai also provides system level test services with parallel system test capabilities up to 320 test sites for all variants of SD, MMC and Memory Stick protocols.
Memory Test Development Services
STATS ChipPAC’s Test Development Center offers extensive development services for Memory Test and testing of 3D devices with Memory components.
Click here to learn more about these services.
Full Turnkey Solutions
When doing business with STATS ChipPAC, the greatest value comes from full turnkey solutions.
Click here to learn more.
Centers of Excellence for Memory Testing
At each of its Centers of Excellence, STATS ChipPAC focuses resources to develop experience and expertise in specific areas of testing. Best practices are developed and proven at these Centers of Excellence for exact copy deployment to STATS ChipPAC’s other factories. In this way, STATS ChipPAC delivers a consistently high level of quality and services across all its factories.
STATS ChipPAC Shanghai (SCC)
STATS ChipPAC Shanghai (SCC) is a Center of Excellence for Flash Memory testing, both single-level cell devices (NOR) and single-level cell and multi-level cell devices (NAND). From MicroSD to SD-USB Plus, the figure below highlights some of the many different Memory Card form factors currently being tested in high volume production at SCC.
STATS ChipPAC Korea (SCK) STATS ChipPAC Korea (SCK) is a Center of Excellence for SRAM, DRAM testing and the testing of 3D packages with a memory component. As a Center of Excellence, SCK has extensive experience and capabilities testing all types of DRAM devices at wafer level, package level and also at system level to confirm the firmware and functionality of the final system.
SCK has also integrated best practices in Flash Memory testing developed at SCC to provide full turnkey advanced packaging solutions with any type of Memory component. As a typical full turnkey solution, SCK tests Flash Memory Wafers on a Memory Test platform, tests a micro-controller wafer on a mixed signal tester, integrates Known Good Memory and controller die into a single package and tests the final memory+controller system on a system level test platform.