Technology

Higher density, better performance, and more efficient integration.

Advanced 2.5D and 3D packaging stacks and interconnects multiple components to maximize functionality and performance.

Package Level Integration

Stacked Die (SD) enables compact multi-die designs.
Package-on-Package (PoP) stacks memory and logic packages.
Package-in-Package (PiP) integrates packaged and bare chips into FBGAs.

Wafer Level Integration

3D wafer level packaging (WLP) with redistribution layers.
eWLB supports high-density connections in 2D, 2.5D, and 3D.
eWLCSP™ enhances CSP reliability, while WLCSP improves density.

Silicon Level Integration

3D IC design eliminates interposers and substrates.
2.5D eWLB enables dense interconnects without TSVs.
2.5D MEOL uses TSVs for cost-effective, high-volume integration.

Powering the next generation of compact, high-performance electronics.

As a leader in wafer level technologies, STATS ChipPAC enables higher density, greater functionality, and scalable manufacturing.

Industry-Leading Solutions

Fan-In Wafer Level Packaging (FIWLP)
Fan-Out Wafer Level Packaging (FOWLP)
Through-Silicon Via (TSV)

Comprehensive Technology Portfolio

Embedded Wafer Level Ball Grid Array (eWLB)
Encapsulated Wafer Level Chip Scale Package (eWLCSP™)
Wafer Level Chip Scale Package (WLCSP)
Integrated Passive Devices (IPD)
Encapsulated Chip Package (ECP)
Radio Frequency Identification (RFID)

Advanced integration for smaller, faster, and more powerful electronics.

System-in-Package (SiP) combines multiple ICs into a compact, high-performance system or modular subsystem. STATS ChipPAC's SiP solutions optimize performance, reliability, and design flexibility.

Double-Sided Molding

Reduces package size and shortens interconnects for improved electrical performance.
Lowers resistance and enhances system efficiency.

Electromagnetic Interference (EMI) Shielding

Uses back metallization to improve thermal conductivity.
Minimizes electromagnetic interference for better signal integrity.

Laser-Assisted Bonding (LAB)

Overcomes traditional reflow bonding issues like CTE mismatch and high mechanical stress.
Increases reliability in high-performance applications.

High-density interconnects, superior performance, and advanced miniaturization.

By soldering the silicon die directly to the substrate, Flip Chip technology improves electrical and thermal performance, reduces parasitics, and enhances power and ground distribution beyond traditional packaging.

Advanced Flip Chip Configurations

Large single-die packages, advanced 3D packaging, and modular solutions.
Cost-effective, high-performance options for diverse applications.

A proven, cost-effective interconnect solution for semiconductor assembly.

Wire bonding reliably connects chips to substrates, substrates to substrates, or substrates to packages, making it one of the most widely used methods in semiconductor manufacturing. STATS ChipPAC offers gold, silver, and copper wire bonding for optimized cost, conductivity, and performance.

Ball Grid Array (BGA)

Uses solder balls for surface mounting, low inductance, and high reliability.
Available in fine pitch, ultra-thin, multi-die, stacked, and thermally enhanced configurations.

Leaded Packages

Cost-effective for simpler applications with traditional through-hole mounting.
Options include:
- Quad Flat Package (QFP)
- Quad/Dual Flat No-Lead (QFN/DFN)
- Thin Small Outline Package (TSOP)
- Small Outline Transistor (SOT)
- Small Outline Package (SOP)
- Dual Inline Package (DIP)
- Transistor Outline (TO)

Smaller, smarter, and built for modern devices.

MEMS and sensors enable miniaturization, integration, and efficiency across communications, consumer electronics, medical, industrial, and automotive applications. STATS ChipPAC offers advanced MEMS packaging solutions designed for high-performance integration, reliability, and cost efficiency.

Comprehensive Turnkey Solutions

Package co-design
Simulation
BOM (Bill of Materials) qualification
Assembly
Quality assurance
In-house testing